Scaling the number of columns for high-resolution image sensors while maintaining the frame rate becomes difficult, as the speed of the readout amplifier trades off with its size, area, and noise performance. One solution is to break the larger sensor into multiple, smaller, charge-mode readout signal paths. In this case, however, the offset of the readout amplifiers will introduce fixed pattern noise, in the form of different offsets for the sub-arrays connected to each readout amplifier.
Input offset storage can be implemented for the readout amplifier by the addition of offset storage capacitors. However, this technique suffers from the additional area required for the capacitors, and the risk of introducing row-correlated noise.